MIPS Single Cycle Datapath

Hi there! While working on Chapter 4 of Computer Organization and Design - The Hardware-Software Interface by Patterson & Hennessy, I decided to create this interactive visualization of the single cycle datapath.

Jump address [31-0]1PC + 4 [31-28]WriteDataReadData 2Result0PCInstruction [20-16]0RegistersDataMemoryControl1Instruction [15-11]Instruction [31-26]Instruction [25-0]Instruction[31-0]InstructionMemoryALUShift-left 2MUXJumpBranchZeroAddressMemReadMemtoRegALUOpALU-ControlMemWriteALUSrcRegWriteReadData 1ReadData 20MUXReadAddress4AddInstruction [15-0]WriteDataMUXInstruction [5-0]MUXWriteRegisterRegDstReadRegister 2Instruction [20-16]ReadRegister 1Instruction [25-21]Shift-left 2ReadData11Sign-extendMUX0Add1PC + 4 [31-28]0 Jump address [31-0] 1 PC + 4 [31-28] WriteData ReadData 2 Result 0 PC Instruction [20-16] 0 Registers DataMemory Control 1 Instruction [15-11] Instruction [31-26] Instruction [25-0] Instruction[31-0] InstructionMemory ALU Shift-left 2 MUX Jump Branch Zero Address MemRead MemtoReg ALUOp ALU-Control MemWrite ALUSrc RegWrite ReadData 1 ReadData 2 0 MUX ReadAddress 4 Add Instruction [15-0] WriteData MUX Instruction [5-0] MUX WriteRegister RegDst ReadRegister 2 Instruction [20-16] ReadRegister 1 Instruction [25-21] Shift-left 2 ReadData 1 1 Sign-extend Sign-extend MUX 0 Add 1 PC + 4 [31-28] 0
Signal value of 1
Signal value of 0
Instruction-dependent

Instruction Formats

R-type instructions add $rd, $rs, $rt

010
rs
rt
rd
shamt
funct
31:26
25:21
20:16
15:11
10:6
5:0

Load/store instruction lw $rt, imm($rs)

3510 (lw)
4310 (sw)
rs
rt
imm
31:26
25:21
20:16
15:0

Branch instruction beq $rs, $rt, imm

410
rs
rt
imm
32:26
25:21
20:16
15:0

Jump instruction j address

210
address
31:26
25:0